1. Field of the Invention
The present invention relates to a semiconductor storage apparatus including cell arrays having a plurality of memory cells, and sense amplifiers.
2. Related Art
As for the conventional one transistor—one capacitor DRAM cell including a trench capacitor or a stacked capacitor, there is a concern that its fabrication may become difficult as it becomes finer. As a candidate for a future DRAM, a new memory cell FBC (Floating Body Cell) is proposed (see Japanese Patent Application Laid-Open Publication Nos. 2003-68877 and 2002-246571). In the FBC, majority carriers are stored in a floating body of an FET (Field Effect Transistor) formed on SOI (Silicon on Insulator) or the like, to store information.
In such a memory cell, an element unit for storing one bit information is formed of only one MISFET (Metal Insulator Semiconductor Field Effect Transistor). Therefore, the occupation area of one cell is small, and storage elements having a large capacity can be formed in a limited silicon area. It is considered that such a memory cell can contribute to an increase of the storage capacity.
The principle of writing and reading for an FBC can be described as follows by taking an N-type MISFET as an example. A state of “1” is defined as a state in which there are a larger number of holes. On the contrary, a state in which the number of holes is smaller is defined as “0.”
The FBC includes an nFET formed on SOI. Its source is connected to GND (0 V) and its drain is connected to a bit line (BL), whereas its gate is connected to a word line (WL). Its body is electrically floating. For writing “1” into the FBC, the transistor is operated in the saturation state. For example, the word line WL is biased to 1.5 V and the bit line BL is biased to 1.5 V. In such a state, a large number of electron-hole pairs are generated near the drain by impact ionization. Among them, electrons are absorbed to the drain terminal. However, holes are stored in the body having a low potential. The body voltage arrives at a balanced state in which a current generating holes by impact ionization balances a forward current of a p-n junction between the body and the source. The body voltage is approximately 0.7 V.
A method of writing data “0” will now be described. For writing “0,” the bit line BL is lowered to a negative voltage. For example, the bit line BL is lowered to −1.5 V. As a result of this operation, a p-region in the body and an n-region connected to the bit line BL are greatly forward-biased. Most of the holes stored in the body are emitted into the n-region. A resultant state in which the number of holes has decreased is the “0” state.
As for the data reading, distinguishing between “1” and “0” is conducted by setting the word line WL to, for example, 1.5 V and the bit line BL to a voltage as low as, for example, 0.2 V, operating the transistor in a linear region, and detecting a current difference by use of an effect (body effect) that a threshold voltage (Vth) of the transistor differs depending upon a difference in the number of holes stored in the body. The reason why the bit line voltage is set to a voltage as low as 0.2 V in this example at the time of reading is as follows: if the bit line voltage is made high and the transistor is biased to the saturation state, then there is a concern that data that should be read as “0” may be regarded as “1” because of impact ionization and “0” may not be detected correctly.
In order to read out data stored in the FBC, a sense amplifier for detecting a current difference between a “0” cell and a “1” cell is provided. The sense amplifier in the conventional FBC has a configuration in which one node is selected from plurality of bit lines BL and sense amplifiers are arranged for the selected nodes. The reason why such a configuration can be adopted is that nondestructive readout is supposed to be possible for the FBC. In other words, the FBC is thought to have a feature that data in cells that are not read are not destroyed even if the word line becomes active and the data continue to be retained as they are if the word line is restored to the retaining level.
In subsequent characteristic evaluation of the FBC, however, it has been found that the FBC is not necessarily a non-destructive read-out cell. Because it has been found that the charge pumping phenomenon affects the characteristics of the cell. If the gate of the transistor is pumped a plurality of times and thereby the inversion state and the accumulation state on the silicon surface are repeated alternately, holes gradually disappear at an interface between the silicon surface and SiO2. This is the charge pumping phenomenon.
The number of holes that disappear due to one state change between inversion and accumulation depends on a density Nit of interface states the Si—SiO2 interface. For example, supposing that Nit=1×1010 cm−2 and W (channel width)/L (channel length) of a cell transistor=0.1 μm/0.1 μm, the area of the Si—SiO2 interface becomes 1.0×10−10 cm2 per cell and consequently the number of interface states per cell becomes approximately one on the average. The number of holes stored in one FBC has a difference of approximately 1,000 depending upon whether the data is “1” or “0”. If the word line WL is subjected to pumping approximately 1,000 times, therefore, data “1” completely changes to data “0”. Practically, if the word line WL is subjected to pumping approximately 500 times, then the readout margin for the data “1” is lost and the risk that a fail may occur becomes high.
In this way, the FBC is neither a destructive read-out cell nor a complete non-destructive read-out cell. It is found that the FBC is so to speak a “quasi non-destructive read-out cell”.
If the sense amplifier circuit of the conventional scheme is applied to such a case, data is not written back even when the word line is activated. If WL is activated during the refresh operation approximately 500 times, therefore, a fail in which data “1” changes to “0” occurs. Irrespective of whether the cell is selected for reading/writing, therefore, it becomes necessary to design a sense amplifier with some measure against the charge pumping phenomenon taken on all “1” data cells for which the word line WL is activated.
Furthermore, such a sense amplifier circuit has a problem of a poor efficiency in the refresh operation as well. In other words, the number of cells that can be refreshed in one refresh cycle decreases to one eighth as compared with an ordinary DRAM in the case where the sense amplifier is connected to a node which are selected from eight BLs. If the refresh time is equal, therefore, it is necessary to conduct the refresh operation as frequently as eight times. By that amount, the proportion in which the ordinary read/write operation cannot be conducted increases.
In addition, there is also a problem that the number of cells that can be accessed is limited when conducting fast column access. In other words, when using a sense amplifier circuit so as to increase the transfer rate of data by activating the word line, reading out cell data, latching the cell data in sense amplifiers, and accessing the data fast and continuously by means of only column address switching, the number of data that can be accessed decreases to one eighth as compared with the ordinary DRAM.
If time required for FBC writing is longer than the cycle time when writing data by using fast column access, then a write fail occurs and this results in a problem that the column access cycle time cannot be made shorter than the FBC write time. Especially, writing FBC data “1” means charging capacitance of the body with holes generated by the impact ionization. If the number of holes generated by the impact ionization is small, therefore, the write time may become as long as approximately several nanoseconds (109 second) or more in some cases.